Targets are Xilinx Kintex7 and intel Arria10 FPGAĪppendix A shows the Xilinx and Intel solutions including:.Do not consider other parameters such as FPGA resource utilization, etc.Design must meet timing constraint, FPGA clock 200Mhz.The goal is to achieve the lowest latency.All inputs are available at the same time in the input of the core.
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This LinkedIn article tries to explain the CPU Software Mentality and the effects of HLS methodology on RTL design by using the following simple example:Įxample: Design a core that compares N=32 single floating point number with a constant number e.g., 0.5 and count the number of cases that satisfy the condition. However, if the HLS developer doesn’t have RTL mentality and knowledge, the result would be poor. This is exactly the reason why HLS tools are interested in RTL planet. Obviously the cost of this high level of flexibility is the fact that RTL design is difficult, time consuming in developing and debugging and therefore expensive. This is a big property that makes RTL mentality and methodology different from CPU software mentality and methodology. By contrast, in the CPU software planet, developers do not need this level of controllability and observability of CPU fixed operations.
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On the other hand, in RTL design one could have several different innovative solution for a unique algorithm. Another property of design in RTL planet is that one could have full control and full observation of the operation of design. On the one hand, the RTL implementation could be sequential logic, combinational logic or combination of them. This sequential mentality comes from the fact that the CPU software developers should follow the sequential rules that are forced by CPU sequential nature.īy contrast, there is high level of flexibility in RTL digital design for implementation of an algorithm. We know that the CPU software developing is sequential mentality which is different by RTL parallel mentality. The first sentence in RTL coding and FPGA/ASIC design courses is: Forget All Your CPU Software Mentality! Methodology of High-Level Synthesis (HLS) compilers.RTL knowledge or RTL Mentality of developers.The answer is hidden within 2 important parameters:
Why the HLS tools with the nature of CPU methodology, in RTL planet don’t have the same performance as RTL tools. In other words, we should ask why the building that is developed by an alien from CPU Software planet sometimes looks tilt in RTL planet.
Why High-Level Synthesis (HLS) tools are not sufficient for FPGA/ASIC design? This is a long-asked question. Bedoustani, Senior FPGA and Real-Time DSP Developer, Montreal, Canada
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